VHDL Specification Methodology from High-level Specification

Specification of Timing Constraints in VHDL for High-Level Synthesis

Reprogrammable Controller Design From High- Level Specification

Existing techniques in high-level synthesis mostly assume a simple controller architecture model in the form of a single FSM. However, in reality more complex controller architectures are often used. On the other hand, in the case of programmable processors, the controller architecture is largely defined by the available control-flow instructions in the instruction set. With the wider acceptanc...

Interface specification and synthesis for VHDL processes

ion levels. This specification is synthesized in accordance with the simulation semantics allowing the validation of the specification and the synthesis result.

Synthesizing Timed Circuits from High Level Specification Languages

This work proposes an efficient methodology to synthesize timed circuits from high level specification languages. In particular, this paper presents a systematic procedure for translating channel-level models to time Petri net descriptions. Care is taken in this translation to guarantee that there are no state coding violations in the resulting nets greatly simplifying the synthesis process. Th...

High-Level Specification of Runtime Reconfigurable Designs

”C to Gates” compilers for FPGAs have been a topic of investigation for nearly two decades. Some of these endeavors have reached a point of viability. Impulse C, for example, enables an application developer to describe hardware using a large subset of standard C. While the Impulse C simulation and implementation tools provide an excellent high-level development environment for FPGA application...